`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:59:34 03/28/2014
// Design Name:   gamelogic
// Module Name:   X:/EC551_project/logic/t_gamelogic.v
// Project Name:  logic
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: gamelogic
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module t_gamelogic;

	// Inputs
	reg clk;
	reg up;
	reg down;
	reg reset;
	reg enemy1_generation;
	reg enemy2_generation;
	reg bullet_generation;

	// Outputs
	wire game_over;
	wire [2:0] lives;
	wire [15:0] scores;
	wire [9:0] xpos_central;
	wire [9:0] ypos_central;
	wire [9:0] xpos_enemy1;
	wire [9:0] ypos_enemy1;
	wire [9:0] xpos_enemy2;
	wire [9:0] ypos_enemy2;
	wire [9:0] xpos_bullet;
	wire [9:0] ypos_bullet;
	wire enemy_signal1;
	wire enemy_signal2;
	wire bullet_signal;
	wire start;

	// Instantiate the Unit Under Test (UUT)
	gamelogic uut (
		.clk(clk), 
		.up(up), 
		.down(down), 
		.reset(reset), 
		.enemy1_generation(enemy1_generation), 
		.enemy2_generation(enemy2_generation), 
		.bullet_generation(bullet_generation), 
		.game_over(game_over), 
		.lives(lives), 
		.scores(scores), 
		.xpos_central(xpos_central), 
		.ypos_central(ypos_central), 
		.xpos_enemy1(xpos_enemy1), 
		.ypos_enemy1(ypos_enemy1), 
		.xpos_enemy2(xpos_enemy2), 
		.ypos_enemy2(ypos_enemy2), 
		.xpos_bullet(xpos_bullet), 
		.ypos_bullet(ypos_bullet), 
		.enemy_signal1(enemy_signal1), 
		.enemy_signal2(enemy_signal2), 
		.bullet_signal(bullet_signal), 
		.start(start)
	);

	initial begin
		// Initialize Inputs
	clk=0;
	#5 reset = 1;
		enemy1_generation=0;
		enemy2_generation=0;
		bullet_generation=0;
	#5 reset = 0;
	
	#5	up = 0;
	#10 enemy1_generation=1;
	#5	down = 0;
	#10 up=1;
	#10 enemy2_generation=1;
	#50 up=0;
	#10 down = 1;
	#10 bullet_generation=1;
	#20 down=0;
	
	// Wait 100 ns for global reset to finish
	#200;
	// Add stimulus here

	end
	
   always #5 clk=~clk;  
endmodule
